ACB control board operation

This document will detail the operation of the SQIID ACB control board.


ACBs - "Array Control Bits" - are signals generated by the sequencer. These signals are all clocked by the sequencer's clock and therefore are all synchronous. The user writes a "microcode" that is downloaded to the sequencer and when commanded, the sequence runs and the ACBs toggle as desired.

The ACB control board takes the sequencer’s ACB outputs and routes them where required, depending upon which array is "selected." ACBs go to the PRCD cards, the preamp cards (as mux selects) and to the ADC converters. Other ACBs go to the coadd/data transfer control board to control the coadder and the IFOT. It should be noted that ACBs that go to the preamp assemblies are driven differentially off of this board.


This board takes a bunch of sequencer ACBs as inputs and generates these ACBs to drive the four arrays as required. Specifically, one can select which array(s) to use, and only those arrays will have active control signals. The others will have their control signals off.

ACBs are generated by the sequencer. A total of fifty-six ACBs are available. The first sixteen bits are active low and the remaining are active high. Sequencer bits change on the rising edge of the sequencer’s Processor Clock Out, which is brought to the backplane as SCLK25. This clock runs at 25 MHz, for a bit time of 40 ns.

Generally, each bit has to be controlled by the sequencer. However, that can quickly complicate matters. For instance, if it is desired to set a bit at the beginning of a long sequence and clear it at the end, the user may not want to have to set that bit on each sequence step. With this in mind, the concept of "latched’ ACBs was invented. Simply put, one can use an ACB as a "latch enable" or "clock enable." When used with external hardware, it is possible to latch the state of one or more ACBs if a "latch enable" ACB is asserted. These latched bits can also be called "slow" bits. Other bits that are not latched can be called "fast" bits.

For SQIID, not only do we have to latch some of the ACBs as required, we also want to be able to control which channel the bits control. For instance, we may want to control the L-channel and read it out while the H, J and K channels are integrating. Therefore, the H, J and K channel control bits won’t toggle whereas the L channel bits will. Two methods of implementing that control come to mind:

First, multiple sequencers. This is problematic in that the in many cases, it is desired to have identical sequences, and the sequencer boards are not capable of being synchronized to another such board.

The second method is to use some of the ACBs as selectors. This is what has been done for SQIID. Four bits are denoted as Array Selects, and a fifth is an Array Select Latch Enable. The sequencer asserts the desired array selects, and then the select latch enable. The FPGA sees that latch enable and stores the selects. These selects are then gated with all of the other ACBs to enable or disable them as needed.

The FPGA on the board handles the array select latching and all of the output ACB generation. SCLK25 is used as the master clock for the FPGA. As noted above, the sequencer changes the ACBs on the rising edge of SCLK25. To ensure reliable operation, all ACBs are registered into the FPGA on the falling edge of that clock (this removes any delay between the change of the clock and the output change) and then immediately registered again on the rising edge of the clock.

If the bit is a "fast" bit, after being synchronized to the clock, it is then ANDed with the array selects and four registered outputs are generated, one for each array channel. The total delay in the FPGA to do this is two clock cycles.

If it is a "slow" bit, after synchonization, the bits are ANDed with the arrays selects, and if the latch enable ACB has been asserted, the new values will be stored in the output registers. Like the fast bits, the total delay is two clock cycles. Thus, all bits are assured of changing at the same time and with the same amount of delay.

After leaving the FPGA, the bits go to differential drivers (if they are used for PRCD/preamp control) or to ‘FCT541 bus drivers (if they are going to the ADC boards). The FPGA’s ACB outputs have pullups or pulldowns, depending on the inactive state of the bit. This is because when the FPGA starts up and is configuring, its outputs are tristated; thus, the bits to the array may be in unknown states during that configuration time.

As a final note, the array activate ACB, ACTV, is an input to this board but it is not input to the FPGA; rather, it simply drives the inputs of two differential drivers, each heading to one of the preamp assemblies.

Design Information

Other details

This board requires +5V at approx. 2A current.

Terminations are installed on all ACB and clock inputs.

The FPGA is configured by the XC9536 and the associated EPROM. Upon startup, the FPGA waits for the XC9536 to serialize the data in the EPROM and download it to the FPGA. The ’74 flipflops act as clock dividers. The configuration process cannot run at the full 25 MHz clock speed so it is divided by four to drive the configuration process. After configuration is complete, the FPGA will turn off the XC9536 and turn on its own outputs and will then be ready to go.

The sequencer reset line is available to be used as a master reset for the FPGA. If the sequencer’s reset is asserted, the FPGA’s internal logic will reset as well. Note that this reset is not a reconfiguration.

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National Optical Astronomy Observatories,
950 North Cherry Avenue, P.O. Box 26732, Tucson, Arizona 85726,
Phone: (520) 318-8000, Fax: (520) 318-8360

This document maintained by Last update: 24 Auigust 1999