| ACB # | Front-Panel Pin | Name | Description | Type | Destination |
|---|---|---|---|---|---|
| 0 | 1 | CTC_L | ADC Convert Start | active-low strobe | ADC |
| 1 | 2 | n/a | n/a | n/a | n/a |
| 2 | 3 | n/a | n/a | n/a | n/a |
| 3 | 4 | n/a | n/a | n/a | n/a |
| 4 | 5 | XCLK_L | clock a digital add on ADC | active-low strobe | ADC |
| 5 | 6 | n/a | n/a | n/a | n/a |
| 6 | 7 | ADCRST_L | ADC Reset | active-low strobe | ADC |
| 7 | 8 | n/a | n/a | n/a | n/a |
| 8 | 9 | n/a | n/a | n/a | n/a |
| 9 | 10 | n/a | n/a | n/a | n/a |
| 10 | 11 | n/a | n/a | n/a | n/a |
| 11 | 12 | n/a | n/a | n/a | n/a |
| 12 | 13 | n/a | n/a | n/a | n/a |
| 13 | 14 | n/a | n/a | n/a | n/a |
| 14 | 15 | ACTV_L | Clock to register BIASEN | active-low strobe | PRCD |
| 15 | 16 | RstLoopSync | Scope Trigger | active-low strobe | front panel |
| 16 | 17 | Read1Sync | Scope Trigger | strobe | front panel |
| 17 | 18 | Read2Sync | Scope Trigger | strobe | front panel |
| 18 | 19 | PxlSync | Scope Trigger | strobe | front panel |
| 19 | 20 | COADD | Do one coadd | strobe | Coadd board |
| 20 | 21 | FRRST | Coadd with 0 instead of buffer data (for a new frame) | latched by ADDSUBEN | Coadd board |
| 21 | 22 | ADDRCLR | Reset buffer address | strobe | coadd board |
| 22 | 23 | ADDSUBEN | clock enable for ADDSUB | strobe (clock enable) | ACB control |
| 23 | 24 | ADDSUB | add=1, subtract=0 | latched by ADDSUBEN | coadd boad |
| 24 | 25 | MEN | PA Mux Select clock enable | strobe (clock enable) | ACB control |
| 25 | 26 | M0 | PA mux select bit | latched by MEN | H, J, K PAs |
| 26 | 27 | M1 | PA mux select bit | latched by MEN | H, J, K PAs |
| 27 | 28 | DXFR | Start Data Transfer | strobe | coadd |
| 28 | 29 | n/a | n/a | n/a | n/a |
| 29 | 30 | FEN | Fast SR clock enable | strobe (clock enable) | ACB control |
| 30 | 31 | F1 | Fast SR Clock 1 | Latched by FEN | PRCD |
| 31 | 32 | F2 | Fast SR Clock 2 | Latched by FEN | PRCD |
| 32 | 33 | FS | Fast SR Clock Sync | Latched by FEN | PRCD |
| 33 | 34 | SEN | Slow SR Clock enable | strobe (clock enable) | ACB control |
| 34 | 35 | S1 | Slow SR Clock 1 | Latched by SEN | PRCD |
| 35 | 36 | S2 | Slow SR clock 2 | Latched by SEN | PRCD |
| 36 | 37 | SOE | Slow SR clock odd/even | Latched by SEN | PRCD |
| 37 | 38 | SS | Slow SR clock sync | Latched by SEN | PRCD |
| 38 | 39 | CREN | Clamp/Reset clock enable | strobe (clock enable) | ACB control |
| 39 | 40 | VRowOn | Row Enable | Latched by CREN | PRCD |
| 40 | 41 | Clamp | Clamp voltage | Latched by CREN | PRCD |
| 41 | 42 | RstR | Row Reset | Latched by CREN | PRCD |
| 42 | 43 | RstG | Global Reset | Latched by CREN | PRCD |
| 43 | 44 | DEN | Row Disable clock enable | strobe (clock enable) | ACB control |
| 44 | 45 | DES1 | Q1 Row Disable | latched by DEN | PRCD |
| 45 | 46 | n/a | n/a | n/a | n/a |
| 46 | 47 | n/a | n/a | n/a | n/a |
| 47 | 48 | n/a | n/a | n/a | n/a |
| 48 | 49 | n/a | n/a | n/a | n/a |
| 49 | 50 | n/a | n/a | n/a | n/a |
| 50 | 51 | n/a | n/a | n/a | n/a |
| 51 | 52 | ARRSELEN | Array Select Clock Enable | strobe (clock enable) | ACB control |
| 52 | 53 | ARRAYHSEL | Array H is selected | latched by ARRSELEN | ACB control |
| 53 | 54 | ARRAYJSEL | Array J is selected | latched by ARRSELEN | ACB control |
| 54 | 55 | ARRAYKSEL | Array K is selected | latched by ARRSELEN | ACB control |
| 55 | 56 | ARRAYLSEL | Array L is selected | latched by ARRSELEN | ACB control |
All strobes are one sequencer-clock-tick (50 ns) wide.