ACB Control board FPGA design sources

The ACB control board FPGA is implemented in a Xilinx XC4005ETQ144-2 device. Synopsys FPGA Express v3.1 was used to synthesize the VHDL source code into an appropriate netlist, and the Xilinx M1.5i (service pack 2) implementation tools were used for place and route.

Note about viewing sources: Your browser may or may not display the code correctly. Netscape will probably complain that the file is of an "unknown file type" and ask you what to do. Internet Explorer will display the code but with wacky tab stops. You may want to download the code and view it in a decent editor with syntax highlighting, like EMACS with the VHDL mode enabled. Set tab stops to 4.

Design Sources

There is only one source file used to create the FPGA:

Test Benches

The following test bench is used to exercise the FPGA:

ACB Control board FPGA simulation timing diagrams

Model Technology's ModelSim PE was used to simulate this design.

The simulation timing diagrams are in Adobe Postscript format. You probably won't be able to view them in your browser. [If anyone knows of a browser plug-in to view Postscript files, please tell me what it is!] Depending on your browser configuration, you may need to save the files and either print them to a postscript printer, or use a tool such as Ghostscript to view them.


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This document maintained by apeters@noao.edu. Last update: 9 July 1999